| 摘要 |
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity with corresponding tag arrays (502(n)), four segments per entry and four valid and dirty bits. Each tag entry (1236) includes task-ID qualifier field (522) and a resource ID qualifier field (520). Data is loaded into various of lines (506) in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag (1236) associated with the data line is set to a valid state (526). In addition to setting a tag to a valid state, qualifier values are stored in qualifier fields (520, 522) in the tag. Each qualifier value specifies a usage characteristic of data stored in an associated data line of the cache. In response to an operation command (1251), each tag in the array of tags that contains a specified qualifier value is modified (1258) in accordance with the operation command. Various types of operation commands can be included in an embodiment of the invention, such as clean, flush, clean-flush, lock, and unlock, for example. |
