| 摘要 |
PROBLEM TO BE SOLVED: To provide a power amplifier that can enhance its gain without incurring increase of the chip size. SOLUTION: A gate bias level Vgg is set so as to hold a relation of Vgg+ΔVin-max>0 and a drain-gate withstand voltage is selected to satisfy a relation of drain-gate breakdown voltage < Vd-bias+ΔVout-max-Vgg+ΔVin- max, whereΔVin-max is a voltage level (a half of a Peak to peak value) at a gate of a MESFET(Metal Semiconductor Field-Effect Transistor) Q1 when the power amplifier provides a maximum power andΔVout-max is a voltage level outputted from the drain of the MESFET Q1 when the power amplifier provides a maximum power. Thus, a negative bias generating circuit is formed at an input of the MESFET Q1 so as to cancel the increase in the gate level by a drain-gate current at an input of a high power thereby increasing the gain without the need for increasing the inter-drain-gate breakdown voltage causing the increase in the chip size.
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