| 摘要 |
<p>The invention relates to a contact structure for a ferroelectric memory device integrated in a semiconductor substrate (5) and comprising an appropriate control circuitry and a matrix array (15) of ferroelectric memory cells, wherein each cell includes a MOS device (3) connected to a ferroelectric capacitor (4); the MOS device (3) having first and second conduction terminals (6A,6B) and being covered with an insulating layer (9); and the ferroelectric capacitor (4) having a lower plate (11) formed on the insulating layer (9) above the first conduction terminals (6A) and connected electrically to the latter, which lower plate is covered with a layer of a ferroelectric material (12) and coupled capacitively to an upper plate (13). Advantageously according to the invention, the contact structure comprises at least a plurality of plugs (10) filled with a non-conductive material between the first conduction terminals (6A) and the ferroelectric capacitor (4), and comprises a plurality of plugs (16) filled with a conductive material for the second conduction terminals (6B) or the control circuitry. <IMAGE></p> |
