| 摘要 |
A semiconductor substrate having a doped well region is provided. A gate stacking structure is formed on the doped well region. The gate stacking structure divides the doped well region into a first area and a second area. The second area is masked. The first area is masked. A spacer is formed on each side wall of the gate stacking structure. A dielectric layer is formed on the semiconductor substrate to cover the gate stacking structure, the spacer, the first doped area, and the second doped area. A via is formed on the dielectric layer. An in-situ doped poly-silicon is utilized to fill the via.
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