| 摘要 |
<p>A method and apparatus for reducing latency in execution of branch instructions are provided. A branch instruction includes an opcode portion (122) and an address portion (128) that includes a displacement (124) and a code (126) that identifies a block in the instruction memory (22) in which the branch target instruction is located. During the fetch cycle in which the branch instruction is fetched, the displacement portion (124) of the branch instruction is reinserted into the address register (20) as the address of the next instruction to be fetched. The code (126) is used to ensure that the address register (20) is pointing to the correct block. As a result, during the next instruction fetch cycle, the target instruction is fetched for execution. Hence, the branch processing latency found in prior systems in which the next fetch cycle is skipped while the branch target address is computed, such as by adding an offset to the program counter (12) value, is eliminated.</p> |
