发明名称 |
DLL lock scheme with multiple phase detection |
摘要 |
A delay lock loop, in accordance with the present invention, includes a plurality of phase detectors each receiving a first clock signal and a second clock signal. Each phase detector includes a specified delay range for detecting phase differences between the first and second clock signals in that range. A delay line includes an input and an output. The first clock signal is received at the input, and the second clock signal includes a delayed first clock signal. An amount of delay is applied to the first clock signal, which is adjusted in the delay line in accordance with control signals of the phase detectors.
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申请公布号 |
US6388482(B1) |
申请公布日期 |
2002.05.14 |
申请号 |
US20000598350 |
申请日期 |
2000.06.21 |
申请人 |
INFINEON TECHNOLOGIES NORTH AMERICA CORP. |
发明人 |
SCHNELL JOSEF;KIEHL OLIVER |
分类号 |
H03L7/081;H03L7/087;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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