发明名称 |
Indexing branch target instruction memory using target address generated by branch control instruction to reduce branch latency |
摘要 |
A processor is provided with an improved instruction buffer, branch target instruction memory, branch target address memory and instruction decoder adapted for handling branch instructions so as to reduce latencies. A branch operation uses both a program branch control instruction (executed in advance to determine the branch target instruction address) and either a conditional or unconditional branch instruction associated with a conditional/unconditional branch target instruction respectively. The conditional/unconditional branch instruction and the program branch control instruction both include separate prediction indicators used by the instruction decoder for initiating a loading and speculatively pre-loading of instructions for execution in the processor.
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申请公布号 |
US6389531(B1) |
申请公布日期 |
2002.05.14 |
申请号 |
US20000690500 |
申请日期 |
2000.10.17 |
申请人 |
HITACHI, LTD. |
发明人 |
IRLE NAOHIKO;WERNER TONY LEE |
分类号 |
G06F9/32;G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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