发明名称 PLL CIRCUIT AND FREQUENCY-DIVIDING METHOD
摘要 PROBLEM TO BE SOLVED: To provide PLL circuit and a frequency-dividing method which allow reduction of spurious noise level, containing in a generating output using a simple configuration. SOLUTION: This PLL circuit performs fractional dividing containing a phase comparator 20 outputting a phase difference signal, in correspondence with phase difference by comparing phases of two signals, a charge pump 21 generating in correspondence with phase difference signals ϕSP, ϕSR, and a low-pass filter 11 and a voltage control generator 12, and which is provided with a control circuit 23, a delay circuit 22 and a selection circuit 24 for modulating the phase difference signal supplied to the charge pump 21.
申请公布号 JP2002135116(A) 申请公布日期 2002.05.10
申请号 JP20000320936 申请日期 2000.10.20
申请人 FUJITSU LTD 发明人 INOUE SHINICHI
分类号 H03L7/085;H03L7/081;H03L7/089;H03L7/197 主分类号 H03L7/085
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