| 摘要 |
PROBLEM TO BE SOLVED: To provide a register controller capable of controlling the data value of a register as expected even when each of plural CPU performs a read modify write cycle to the same register at any timing. SOLUTION: When a CPU 11 is to set the data value of an arbitrary bit in a TIER register 14 to '1' by performing a bit operating instruction, data are read by accessing a TIER1W register 16 in the first half read cycle of a RMW cycle and when the write cycle is performed in the address of the TIER1W register 16 after the data value of the change target bit is turned into '1', concerning the bit of the data value changed to '1', that data value '1' is outputted to a master latch 18 of the TIER register 14 by a multiplexer 17 but concerning the other bits, the held data in a slave latch 19 are selected to be outputted.
|
