| 摘要 |
PROBLEM TO BE SOLVED: To provide a driving circuit of a configuration in which the timing for holding a picture signal in a latch circuit is not influenced by a delay in a sampling pulse. SOLUTION: A digital picture signal is held by turning on a pre-charge TFT 102 within a blanking interval to bring the input terminal of a holding part 101 into a potential Hi (VDD), and turning on all of TFTs 104-106 when the three signals of a sampling pulse, an external input multiplex signal, and a digital signal are all inputted, to bring the input terminal potential of the holding part 101 into a potential Lo. A sampling pulse width is wider than the pulse widths of the two external input signals, and the output periods of the two external input signals are completely included in the output period of the sampling pulse, therefore, even if a slight delay occurs on the sampling pulse, it does not have an influence on the timing for the holding but it is possible to easily decide the timing for the holding. |
