Halbleiter-Anordnung und Verfahren zur Herstellung von derartigen Halbleiter-Anordnungen

摘要

An interposer (IP) comprised of an elastic dielectric is formed on the active surface of a semiconductor wafer, whereby electrically conductive connections (V) that are formed inside the interposer (IP) connect, in an electrically conductive manner, chip-side contacts (K) with terminals (A) on the top surface (OS) of the interposer (IP). The individual semiconductor assemblies (HA) subsequently result by dividing up the semiconductor wafer. The different thermal expansion behavior of the chip (C) and of the circuit support is largely compensated for by the elasticity of the interposer (IP) and by the preferably meandering design of the connections (V).