| 摘要 |
There is disclosed a voltage level shifter that receives an input signal having a maximum Logic 1 value of VDD and produces an output signal having a maximum Logic 1 value of VDDI/O, where VDDI/O is greater than VDD. The voltage level shifter comprises: 1) a first circuit branch comprising A) a first p-type transistor having a source coupled to a first power supply having a level of VDDI/O and B) a first n-type transistor having a source coupled to ground, a drain coupled to a drain of the first p-type transistor, and a gate coupled to the input data signal; and 2) a second circuit branch comprising A) a second p-type transistor having a source coupled to the first power supply and a gate coupled to a drain of the first n-type transistor and B) a second n-type transistor having a source coupled to ground, a drain coupled to i) a drain of the second p-type transistor and ii) a gate of the first p-type transistor, and a gate coupled to an inverted copy of the input data signal, wherein a drain current of the first p-type transistor is larger than a drain current of the second p-type transistor for the same gate-to-source voltage, such that the first p-type transistor turns on faster than the second p-type transistor if the first power supply is powered up to VDDI/O when the first and second n-type transistors are off.
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