| 摘要 |
A memory test circuit having access control circuits (11 and 12, or 21 and 22, or 31 and 32) recognizes a first memory circuit (101) and a second memory circuit (102), as one continuous memory, incorporated in a semiconductor processing device based on addresses and control commands provided from an external device. The memory test circuit then executes a memory test operation for the first and second memory circuits (101 and 102) continuously.
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