| 摘要 |
An absolute encoder that can generate an absolute value signal by performing simple operation processing. Phase signals phi0 to phi3 are represented by j-bit digital signals, a signal b provided by dividing the phase signal phi0 by 2K1 (where K1 is an integer) is subtracted from a phase difference signal phi01=c, an absolute value signal A01=f of the number of pitches (a0-a1) with a signal of the high-order K1 bits of the signal provided by subtracting the signal from phi01 as high-order bits and phi0 as low-order bits, subsequently a signal g provided by dividing the phase signal A01=f by 2K2 (where K2 is an integer) is subtracted from a phase difference signal phi02=h, an absolute value signal A02=k of the number of pitches (a0-a2) with a signal of the high-order K2 bits of the signal provided by subtracting the signal from phi02 as high-order bits and f as low-order bits, and the process is executed in order, whereby a longer-pitch absolute value signal is generated and signals are processed in order from the shorter-pitch signals to the longer-pitch signals, whereby the condition under which the pitch number cannot be determined is eliminated, and a large allowance of a phase error between slits can be taken. An error of a phase difference signal at the high-speed scale rotation time can also be corrected and adjusted by PLL.
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