| 摘要 |
A linear phase detector circuit enables locking of two frequency sources which can operate in the range of 10 GHz with a minimal frequency offset, such as from 0 Hz to 50 KHz. With the frequency sources operating at frequencies F1 and F2 with an offset F2-F1 or F1-F2, the phase detector generates a DC signal indicating a phase offset between a signal F2-F1 or F1-F2 derived from the frequency sources and a reference operating at the desired offset F2-F1 or F1-F2, while eliminating any 2(F2-F1) or 2(F1-F2) component. In this way, the phase detector allows a substantially higher loop bandwidth than the offset F2-F1 or F1-F2, and allows phase tracking independent of the offset. The phase locking circuitry is useful in applications such as providing a variable Doppler shift in a radar signal.
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