| 摘要 |
A memory cell is defined along first, second, and third orthogonal dimensions and comprises an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact. The charge storage structure is conductively coupled to the bit line via the transistor structure and the bit line contact. The transistor structure is conductively coupled to the word line. The first dimension is characterized by one-half of a bit line contact feature, one word line feature, one word line space feature, and one-half of a field poly line feature. The second dimension is characterized by two one-half field oxide features and one active area feature. The first and second dimensions define a 6F2 memory cell. The bit line contact feature is characterized by a contact hole bounded by insulating side walls. The insulating side walls comprise a first pair of opposing insulating side walls along the first dimension and a second pair of opposing insulating side walls along the second dimension. The first pair of opposing insulating side walls comprise respective layers of insulating spacer material formed over a conductive line. The second pair of opposing insulating side walls comprise respective layers of insulating material formed between respective contact holes. The contact hole is filled to an uppermost extent of the insulating side walls with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile in contact with the bit line. The memory cell may further comprise a storage node characterized by a storage node contact hole filled with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile.
|
