发明名称 WIRING METHOD FOR SEMICONDUCTOR PACKAGE
摘要 PROBLEM TO BE SOLVED: To provide a wiring method for a semiconductor package which can decrease the man-hour needed for wiring design and design wiring between terminals at optimum intervals. SOLUTION: This method includes a step where wiring routes connecting via parts 12 individually are roughly wired with segments, a step where a wiring pattern 16 is generated by molding so that the segments do not interfere with one another and have optimum wiring intervals, a step where a fine segment 15 shorter than specific length at the molded wiring part is scanned and searched for and deleted, and a step where the wiring pattern 16 is corrected by redrawing a segment so that the wiring ends having the fine segment 15 deleted are electrically connected.
申请公布号 JP2002123564(A) 申请公布日期 2002.04.26
申请号 JP20000312013 申请日期 2000.10.12
申请人 SHINKO ELECTRIC IND CO LTD 发明人 ICHIMURA TAKAHIDE;KITAMURA TAMOTSU;SAKAI HIROYUKI
分类号 G06F17/50;H01L23/12;(IPC1-7):G06F17/50 主分类号 G06F17/50
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