发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit which detects the noise of an analog power supply and generates an alarm and which comprises the check means of the analog power supply capable of preliminarily preventing the problem that the phase of an output waveform is not fixed. SOLUTION: In the PLL circuit, the check means 4 is installed. In the check means 4, a first potential comparison circuit 23 which outputs a high-level signal when the maximum potential of the analog power supply is higher than a first comparison potential is installed, a second potential comparison circuit 25 which outputs a low level signal when the minimum potential of the analog power supply is lower than a second comparison potential is installed, an inverter 26 to which an output signal from the circuit 25 is input and which inverts the output signal so as to be output is installed, an OR circuit 27 to which an output signal from the inverter 26 and an output signal from the circuit 23 are input and which outputs the logical sum of the signals is installed, and a flip-flop circuit 29 to which the logical sum is input and which outputs an alarm signal when the logical sum is at a high level so as to operate the alarm 5 is installed.
申请公布号 JP2002124870(A) 申请公布日期 2002.04.26
申请号 JP20000311335 申请日期 2000.10.11
申请人 NEC CORP 发明人 KAMIYA HIROSHI
分类号 H02H7/20;G01R19/165;H02H3/44;H03L1/00;H03L7/08 主分类号 H02H7/20
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