发明名称 PROCESSOR CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD
摘要 <p>PROBLEM TO BE SOLVED: To provide a processor clock generating circuit and a clock generating method for designing a low-power-consumption CDMA modem chip. SOLUTION: The processor clock signal generating circuit for a modem chip includes a 1st clock generation part 110 which generates a 1st clock signal according to enable and disable signals, a 2nd clock generation part 120 which generates a 2nd clock signal having a lower frequency than the 1st clock signal, a decoder which decides which of power-down instruction word or and power-up instruction word an instruction word inputted from outside is by decoding the inputted instruction word and generates a control signal, a clock selection part 140 which outputs one of the 1st and 2nd clock signals as a processor clock signal, and a 1st clock control part 130 which activates or inactivates the generation of the 1st clock signal.</p>
申请公布号 JP2002123330(A) 申请公布日期 2002.04.26
申请号 JP20010246183 申请日期 2001.08.14
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 KIM DONG-YUN
分类号 H04L7/00;G06F1/04;G06F1/32;(IPC1-7):G06F1/04 主分类号 H04L7/00
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