| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a method and device for laying out an integrated circuit permitting to realize shortening a development period by eliminating iteration for securing an opening ratio. SOLUTION: This device reads an opening area of each standard cell (S4), and calculates an opening area of the part of the standard cells (S6) of the whole chip by extracting the number of the standard cells and the kinds thereof from actual layout data (S5). Moreover, the device extracts information such as a length and a kind of the wiring from the actual data (S7, 8), and calculates an opening area of the wiring part (S9). The device calculates an opening ratio of the whole chip from the above two opening areas and the chip size (S10), and decides the opening ratio (S12) by inputting opening ratio limit conditions thereto (S11). When the opening ratio does not satisfy the limit conditions, corrections are made to secure the opening ratio without necessity for converting a data format (S13). Thus, it is possible to perform from the calculation of the opening ratio up to its corrections on a same data format, therefore, iteration is eliminated and a development period can be shortened.</p> |
