Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester

摘要

A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial-parallel conversion circuits subjecting received, packetized data to serial-parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.