Processor architecture with variable-stage pipeline

摘要

An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages (IF, ID, EX, MEM, WB) and a network of forwarding paths (EX-EX, MEM-EX, MEM-ID) which connect pairs of said stages, as well as a register file (RF) for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing (Write inhibit) and subsequent readings in said register file (RF) of operands retrievable from said forwarding network on account of their reduced liveness length.