发明名称 Allocation of hardware accelerators
摘要 A data processing system 10 comprising a plurality of processors, a first controller that allocates data to one of a plurality of time frames and a second controller that allocates data associated with a particular time frame to a particular processor for processing, with the aim of minimising data transfer between processors. The processors may be connected via a matrix 13 to re-configurable logic blocks or accelerators 11, and preferably there are twice as many accelerators as processors. The processors may be DSPs, ASICs or ASSPs. Preferably the system, and associated method, are for use in a mobile communications terminal such as a mobile phone where data via received in air interface timeslots.
申请公布号 GB0205817(D0) 申请公布日期 2002.04.24
申请号 GB20020005817 申请日期 2002.03.12
申请人 TOSHIBA RESEARCH EUROPE LIMITED 发明人
分类号 G06F9/50 主分类号 G06F9/50
代理机构 代理人
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