摘要 |
The present invention relates to a phase-locked loop (PLL) circuit performing a fractional division which circuit includes a phase comparator circuit (20), a phase difference signal modulation circuit, and an oscillator circuit. The phase comparator circuit (20), compares phases of two signals (fr, fp) and outputs first and second phase difference signals ( d P1, d R1, d P2, d R2). The phase difference signal modulation circuit modulates the second phase difference signals into third phase difference signals, and the oscillator circuit oscillates based on the first and third signals. |