| 摘要 |
Memory blocks provided to share a sense amplifier band, a global IO (GIOB) bus provided in common to the memory blocks for transferring internal data, and local IO bus lines provided corresponding to the memory blocks are connection-controlled based on signals related to a column select operation. Driving memory blocks independently from each other permits each memory block to be used as a bank, and if one memory block is accessed during activation of another memory block, data can be prevented from colliding on the global IO bus. A main memory with high page hit rate is implemented using a semiconductor memory device with a shared-sense amplifier configuration. When a first memory block sharing a sense amplifier coupled to a second memory block is addressed, the second memory block is inactivated, and then the addressed first memory block is accessed, when a valid data is output, such valid data outputting is signaled by a data valid signal.
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