| 摘要 |
The detection circuit comprising: a first D-type flip-flop circuit F/F1, to which the data signal D1 and the clock signal C1 are input; a first delay circuit DL2 which delays the clock signal C1 by a prescribed amount of time, so as to generate a delayed clock signal C1'; a second D-type flip-flop circuit F/F2, to which the output signal Q1 of the first D-type flip-flop circuit F/F1 and the delayed clock signal C1' are input; a second delay circuit DL1 which delays the an output signal Q2 of the second D-type flip-flop circuit F/F2 so as to generate a first delayed signal Q2', a third delay circuit DL3 which delay the an output signal Q1 of the first D-type flip-flop circuit F/F1 so as to generate a second delayed signal Q1', a fourth delay circuit DL4 which delays the data signal D1 so as to generate a delayed data signal D1', a first AND circuit AND2 which calculates a logical product of the first delayed signal Q2' and the second delayed signal Q1' so as to output a DOWN signal, a second AND circuit AND1 which calculates a logical product of the second delayed signal Q1' and the delayed data signal D1' so as to output an UP signal, and an adder circuit ADD which adds the UP signal and the DOWN signal so as to output a detection signal PDOUT detecting the phase difference between the data signal D1 and the clock signal C1.
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