| 摘要 |
The invention includes a first flip-flop (FF) 2 for taking in a clock signal CLK output of a voltage control oscillator 1 at a leading or trailing edge of a data signal to then output it, a delay circuit 3 for delaying the clock signal output of the voltage control oscillator by 90.degree. a second FF4 for taking in the clock signal delayed at the delay circuit 3 at leading or trailing transition timing of the data signal to then output it, a logical product circuit 5 for AND'ing an output of the second FF and the clock signal CLK90 delayed by the delay circuit, a third FF6 for taking in an output of the first FF at leading or trailing transition timing of an output of the logical product circuit 5 to then output it, and an average detector circuit 7 for detecting a time-wise average of an output of the third FF6, an output voltage of which circuit 7 is fed back to a control terminal of the voltage control oscillator.
|
