BASIC CELL, INTEGRATED CIRCUIT LAYOUT SECTION, INTEGRATED CIRCUIT LAYOUT, INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING SIGNAL LINE OF INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a basic cell for designing a gate array or a standard cell integrated circuit. SOLUTION: The basic cell for designing a gate array or a standard cell integrated circuit has N and P wells arranged in checker board pattern wherein each well includes P and N devices. A plurality of first relatively deep P regions abut on at least a plurality of first and second relatively deep N regions, the first relatively deep N region abuts on the first relatively deep P region along the first edge of the first relatively deep N region and the second relatively deep P region along the second edge of the second relatively deep N region wherein the first and second edges of the relatively deep N region are perpendicular. The basic cell array has a checker board pattern and is suitable for minimizing the clock parasitic capacitance at the time of laying out a clocked inverter at the apex of the checker board pattern.