| 摘要 |
PROBLEM TO BE SOLVED: To provide a fabrication method of a bipolar transistor for reducing an emitter-base parasitic capacity, hence reducing the entire capacity, achieving the higher operating speed of an integrated circuit, and easily incorporating into an existing complementary metal oxide semiconductor(CMOS) technique without increasing the number of devices, price, or manufacturing time. SOLUTION: The bipolar transistor that is arranged on a semiconductor wafer substrate is provided. The bipolar transistor may contain a collector that is arranged in the semiconductor wafer, a base that is arranged in the collector, and an emitter that is arranged on the base and comes into contact with at least one portion of the base, and the emitter has a low-K layer inside. The low-K layer may be arranged, for example, close to one side of the emitter or close to the opposing side of the emitter. However, in all embodiments, the low-K layer does not interfere with the appropriate functions of the bipolar transistor and essentially reduces an emitter-base capacity that typically accompanies a conventional bipolar transistor.
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