发明名称 |
METHOD TO REDUCE TIMING SKEWS IN I/O CIRCUITS AND CLOCK DRIVERS CAUSED BY FABRICATION PROCESS TOLERANCES |
摘要 |
A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.
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申请公布号 |
US2002044011(A1) |
申请公布日期 |
2002.04.18 |
申请号 |
US19990473855 |
申请日期 |
1999.12.28 |
申请人 |
DABRAL SANJAY;SESHAN KRISHNA |
发明人 |
DABRAL SANJAY;SESHAN KRISHNA |
分类号 |
G06F13/40;H01L21/8234;H01L21/8238;H01L29/423;H03L7/00;(IPC1-7):H03L7/00 |
主分类号 |
G06F13/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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