发明名称 |
Bit synchronization circuit |
摘要 |
A bit synchronization circuit operates at high speed range as high as Gb/s or higher and can establish synchronization within 10 bits with rejecting jitter to permit accurate bit synchronization. The bit synchronization circuit thus generates a plurality of clocks having mutually different phases in synchronism with an input reference clock. A phase relationship between a plurality of clocks and an input data to be decided is discriminated by a phase comparator circuit. The clock having optimal phase relationship, namely clock having level transition timing having at a substantially center portion of mutually adjacent level transition timing of the input data, is determined by a phase determination circuit. An decision circuit and selector are provided for deciding input data at the level transition timing of the determined clock.
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申请公布号 |
US6373911(B1) |
申请公布日期 |
2002.04.16 |
申请号 |
US19990239090 |
申请日期 |
1999.01.27 |
申请人 |
NEC CORPORATION |
发明人 |
TAJIMA AKIO;SUEMURA YOSHIHIKO;ARAKI SOICHIRO;TAKAHASHI SEIGO;MAENO YOSHIHARU;HENMI NAOYA |
分类号 |
H03L7/081;H04L7/00;H04L7/02;H04L7/033;H04L7/10;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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