发明名称 Transient testing in electronic integrated circuits, uses variable delay circuit to provide clock signals for memory circuits which hold output from circuit under test
摘要 The test circuit delivers test signals (10) to a circuit under test (4). A source of profiles (1) is driven by the signal source and connects to the test circuit. A variable delay (12) driven by the signal source provides the clock signal both to a memory (6) connected to the test circuit, and to a second memory (8) receiving its input from the first memory (6).
申请公布号 FR2814876(A1) 申请公布日期 2002.04.05
申请号 FR20010011093 申请日期 2001.08.24
申请人 SCHLUMBERGER TECHNOLOGIES INC 发明人 WEST BURNELL G
分类号 G01R29/02;G01R31/28;G01R31/30;G01R31/317;G01R31/319;G01R31/3193;(IPC1-7):H04B17/00;G06F11/22 主分类号 G01R29/02
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