| 摘要 |
PURPOSE: A data path verifying circuit is provided to be capable of detecting an erroneous region on a data input/output path. CONSTITUTION: An even data receiving part(20) receives even data(WD0, WD2, WD4, WD6) of input data(WD0-WD7) at a low-to-high transition of a control clock(CLK). The first selector(26) transfers an output signal of the receiving part(20) to an even multiplexer(22) in a normal mode, and to an odd multiplexer(23) via the first path in an even data test mode. The even multiplexer(22) transfers an output of the first selector(26) to the second selector(28) in the normal mode, and transfers an output of the third selector(27), received via the third path, to the second selector in an odd data test mode. The second selector(28) transfers an output of the even multiplexer(22) in the normal mode, and transfers an output of the even multiplexer(22) to an odd pipeline(25) through the second path. The first clock selector(30) receives the first control signal(C1), the second control signal(C2), the control clock(CLK), and an inverted control clock(CLKb), and selects the inverted control clock in the normal mode and the control clock(CLK) in the even data test mode. The selected signal is supplied to the odd pipeline(25). The even pipeline(24) receives an output of the second selector or an output of the fourth selector(29) via the fourth path, and outputs four-bit parallel data according to an output signal of the second clock selector(31). An even data receiving part(21) receives odd data(WD1,WD3,WD5,WD7) of the input data(WD0-WD7) at a low-to-high transition of the inverted control clock(CLKb). The third selector(27) transfers an output signal of the receiving part(21) to an odd multiplexer(23) in the normal mode, and to the even multiplexer(22) via the third path in the odd data test mode. The odd multiplexer(23) transfers an output of the third selector(26) to the fourth selector(29) in the normal mode, and transfers an output of the first selector, received via the first path, to the fourth selector in the even data test mode. The fourth selector(29) transfers an output of the odd multiplexer(23) in the normal mode to an odd pipeline(25), and transfers an output of the odd multiplexer(23) to the even pipeline(24). The second clock selector(31) receives the third control signal(C3), the fourth control signal(C4), the control clock(CLK), and the inverted control clock(CLKb), and selects the control clock in the normal mode and the inverted control clock in the odd data test mode. The selected signal is supplied to the even pipeline(24). The odd pipeline(25) receives an output of the fourth selector or an output of the second selector(28) via the second path, and outputs four-bit parallel data according to an output signal of the first clock selector(30).
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