METHOD FOR DESIGN VALIDATION OF COMPLEX IC

摘要

PURPOSE: A method for design validation of a complex IC is provided to evaluate and validate the design of a complex IC such as a system-on-a-chip with use of a combination of electronic design automation(EDA) tools and an event based test system with high speed and low cost. CONSTITUTION: The method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.