| 摘要 |
A semiconductor storage device that can be selectable between input/output (I/O) configuration and have reduced area for data buses and/or reduced number of circuit elements is disclosed. According to one embodiment, a semiconductor storage device may include first and second memory cell arrays (10 and 12). Eighteen first sense amplifiers (SA(L)1-18) can be connected to the first memory cell array (10) and eighteen second sense amplifiers (SA(R)1-18) can be connected to the second memory cell array (12). In addition, eighteen first I/O circuits (I/O(L)1-18) may correspond to the first sense amplifiers (SA(L)1-18) and eighteen second I/O circuits (I/O(R)1-18) may correspond to the second amplifiers (SA(R)1-18). Eighteen data buses (DB1-DB18) can be situated between the sense amplifiers (SA(L)1-18 and SA(R)1-18) and I/O circuits (I/O(L)1-18 and I/OR)1-18). Each data bus may be separated into at least two different portions by a disconnecting device (T1-T18). In one I/O configuration (e.g., x36), disconnecting devices (T1-T18) separate the data buses (DB1-DB18) into two different portions, in another I/O configuration (e.g., x18) the data buses (DB1-DB18) are not separated into different portions.
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