发明名称 Selecting circuit, digital/analog converter and analog/digital converter
摘要 A pair of internal signals are generated by halving a 3-bit 5-valued input signal, neglecting the least significant bit LSB. If the input signal shows the value of an odd number, 1 is added to either of the pair of internal signals to generate first and second signals. "1" is added to either of the pair of internal signals in an alternating way each time an input signal having the value of an odd number. Signal processing circuits selects a number of output terminals corresponding to the value of the first signal or the second signal out of a plurality of output terminals. All the output terminals are selected with a same probability.
申请公布号 US6366228(B2) 申请公布日期 2002.04.02
申请号 US20010817044 申请日期 2001.03.27
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 NAGATA MITSURU
分类号 H03M1/74;H03M1/06;H03M1/12;H03M3/00;(IPC1-7):H03M1/66 主分类号 H03M1/74
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