METHOD FOR FABRICATING GATE ELECTRODE HAVING LARGE SILICIDE REACTION AREA

摘要

PURPOSE: A method for fabricating a gate electrode which increases a silicide reaction area is provided to increase an area where a polysilicon layer pattern reacts with high-melting metal, by exposing the upper surface of the polysilicon layer pattern and a side surface of the upper portion of the polysilicon layer pattern. CONSTITUTION: A polysilicon layer is formed on a semiconductor substrate(100), and is patterned to form the polysilicon layer pattern. The first insulation layer is formed on the substrate including the polysilicon layer pattern, and is etched back to form a spacer on the sidewall of the polysilicon layer pattern. An etch stop layer(120) having the same etch rate as the first insulation layer and the second insulation layer having high etch selectively regarding the first insulation layer and the etch stop layer are sequentially formed on the substrate having the spacer. The second insulation layer is etched until the upper surface of the etch stop layer is exposed. An etch process is performed regarding the substrate to form a groove(124) exposing the upper surface of the polysilicon layer pattern and the upper portion of the sidewall of the polysilicon layer pattern by using a mask. The high-melting metal is formed on the substrate having the groove. The high-melting metal is annealed to form a high-melting silicide layer on the upper surface of the polysilicon layer pattern and on the upper portion of the sidewall of the polysilicon layer pattern.