SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory which can perform high speed operation by suppressing phase deviation between output data and an echo signal without sacrificing a cycle time and a data output time. SOLUTION: An address register 5 and a data register 7 are controlled by a clock taken by a clock buffer 9, and synchronism of read-out/write-in of data of a normal array 1 is controlled. The device is provided with a memory cell array 1a for echo signal which shares a word line with the normal cell array 1 and in which an expected value pattern is written. The device is provided with a read-out/write-in circuit 6a for echo signal and a data register 7a for echo signal which are arranged respectively in parallel to the read-out/ write-in circuit 6 and the data register 6 of the normal cell array 1 side and has the same constitution at the memory cell array 1a for echo signal side.