发明名称 RECEIVING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a receiving circuit capable of generating an optimum reference potential for correctly deciding the logical level of a signal deteriorated by a simple clock signal by using about 1 to 2-bit past data series that are small. SOLUTION: This receiving circuit is provided with a circuit for predicting the signal level of the present point of time from the signal level and logical decision value of the point of time ahead of one bit or several bits, transmitted to a signal transmission line, or the time series of the average value and logical decision value of a signal level from the time ahead a fixed point of time up to the present point of time, and generating the optimum logical decision level at the present point of time. A low power consumption system having small latency can be constructed because past data series needed to correctly decide a signal are minimized. A large effect can be expected for reduction in system cost because a transmitting medium which is expensive and has a large mounting size is not needed.
申请公布号 JP2002094577(A) 申请公布日期 2002.03.29
申请号 JP20000283180 申请日期 2000.09.19
申请人 NEC CORP 发明人 MAETA TADASHI
分类号 G06F3/00;H03K5/08;H03K19/0175;H03M1/12;H04L25/02;H04L25/03;H04L25/06;(IPC1-7):H04L25/03;H03K19/017 主分类号 G06F3/00
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