发明名称 COMPLEX VALUED DELTA SIGMA PHASE LOCKED LOOP DEMODULATOR
摘要 <p>The demodulator is a multiple stage demodulator. The first stage is a conversion stage which converts an incoming signal into a first complex representation. The second stage is a direct digital synthesizer (DDS)/mixer which synthesizes a signal to be mixed with the first complex signal and performs the mixing operation to produce a second complex output. This secon d complex signal is controlled by a bitstream fed back from the third stage - a phase quantizer stage. The bitstream represents the quantized phase differen ce between the synthesized signal and the first complex signal. The DDS/mixer stage then measures the synthesized signal for any phase difference from the incoming signal through the feedback inherent to a PLL, the bitstream thus provides an output that gives the frequency of the desired signal. As a side benefit, the real component of the second complex signal, provides an amplitude estimate of the desired signal.</p>
申请公布号 CA2422794(A1) 申请公布日期 2002.03.28
申请号 CA20012422794 申请日期 2001.09.19
申请人 RILEY, TOM 发明人 RILEY, TOM
分类号 H03D3/00;H03D7/16;(IPC1-7):H03D3/00;H04L27/233 主分类号 H03D3/00
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