Decoder for memories having optimized configuration

摘要

A decoder with reduced complexity includes at least one OR circuit section and at least one AND circuit section. The at least one OR circuit section may include first and second circuit lines mutually connected and respectively receiving as inputs an address signal and an inverted address signal. The at least one AND circuit section may include first and second circuit lines which respectively receive as inputs the inverted address signal and the address signal. The at least one OR circuit section and the at least one AND circuit section may be connected to first and second booster circuits. Furthermore, the at least one OR circuit section may also include a virtual ground.