CONTROLLER HAVING MAIN MICROPROCESSOR AND PROCESSOR INTERFACE TO BUS TRANSMITTING/RECEIVING UNIT

摘要

PROBLEM TO BE SOLVED: To prevent apparently valid data from being transmitted and received through a data bus by a simple and low-cost method. SOLUTION: This controller is provided with a means for resetting the data contents of a transmission memory (8) and/or the data contents of a reception memory (9) after each output and/or each read of data memorized there in a definition state ('invalid marking'), before a main microprocessor (4) outputs and/or reads new data.