发明名称 VITERBI EQUALIZING DEVICE
摘要 PROBLEM TO BE SOLVED: To estimate a receiving timing with high accuracy. SOLUTION: A correlation value between digital I and Q signal columns, stored in a reception signal buffer 101 and an known symbol column inserted into a p prescribed position is calculated by a vector arithmetic operation, and a receiving timing is estimated by sampling rate units according to the position, where the value is maximized. The rate of the estimated timing to the correlation value in one preceding sample is calculated and compared with the table value of the value of the rate preliminarily calculated at each fine time interval, so that the position where the difference is minimized can be calculated. Thus, the receiving timing can be estimated more accurately than for the sampling rate, based on this position.
申请公布号 JP2002084333(A) 申请公布日期 2002.03.22
申请号 JP20000269817 申请日期 2000.09.06
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ABE KATSUAKI;ORIHASHI MASAYUKI;JOB KLEOPA MUSUYA
分类号 H03M13/41;H04B3/06;H04B7/005;H04L7/00;H04L27/38 主分类号 H03M13/41
代理机构 代理人
主权项
地址