发明名称 Buffer controller
摘要 A method and apparatus for accessing successive memory locations without the need for multiple index register writes and without the need for a wide address bus from the controller into a memory control system. The memory control system includes an index register and a data register. The index register has a connection to the controller and the buffer. The data storage register has a connection to the buffer and to the controller. The index register receives an address to a location in the buffer. Each time the contents of the index register are changed, data associated with the address are automatically written into the data storage register. Each time the data storage register is accessed (read or written), the index register in incremented. The controller is able to read or write unlimited numbers of sequential locations up to the full buffer space, using only a single controller access per byte.
申请公布号 US6360308(B1) 申请公布日期 2002.03.19
申请号 US19980163835 申请日期 1998.09.30
申请人 LSI LOGIC CORPORATION 发明人 FECHSER DAVID A.
分类号 G06F3/06;G06F9/345;G06F9/355;(IPC1-7):G06F12/00 主分类号 G06F3/06
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