发明名称 SOFT OUTPUT DECODER AND SOFT OUTPUT DECODING METHOD AND DECODER AND DECODING METHOD
摘要 PROBLEM TO BE SOLVED: To achieve decoding of an arbitrary code through a simple arrange ment. SOLUTION: In a soft output decoding circuit of an element decoder, a circuit 161' for calculating a logarithmic soft output I /1 calculates the sum of logarithmic likelihoods Iα, Iγand Iβcorresponding to respective branches on a trellis, selects a relevant branch depending on the I/O pattern of each branch, and calculates a logarithmic soft output Iλby performing an operation comparable to a tournament. More specifically, the soft output calculating circuit 161' selects a relevant branch depending on the I/O pattern of each branch on the trellis previously from data AGB of thirty two systems through a selection circuit 590, performs log-sum operation through log-sum operating circuits 5911,..., 5918 using the data AGB of selected sixteen systems and outputs the data AGB selectively from seven log-sum operating circuits thus realizing cumulative addition of log-sum operation depending on the input.
申请公布号 JP2002076942(A) 申请公布日期 2002.03.15
申请号 JP20000263129 申请日期 2000.08.31
申请人 SONY CORP 发明人 YAMAMOTO KOHEI;MIYAUCHI TOSHIYUKI
分类号 G06F11/10;H03M13/23;H03M13/27;H03M13/29;H03M13/39;H03M13/41;H03M13/45;(IPC1-7):H03M13/45 主分类号 G06F11/10
代理机构 代理人
主权项
地址