发明名称 FAILURE ANALYSIS METHOD OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide an effective etching method for LSI failure analysis. SOLUTION: In failure analysis of a semiconductor device of which the failure cause is due to a metal wiring formed on a semiconductor silicon substrate, by combination of a wet etching and a dry etching, the surface of the upper layer metal wiring 5 is damaged by a wet etching. Then, by applying a dry etching on it, only metal wiring 5 to be removed can be removed.
申请公布号 JP2002076084(A) 申请公布日期 2002.03.15
申请号 JP20000255686 申请日期 2000.08.25
申请人 SANYO ELECTRIC CO LTD 发明人 KANEKO MAMORU;ITABASHI ATSUSHI
分类号 G01N1/32;G01N1/28;H01L21/302;H01L21/306;H01L21/3065;H01L21/3205;H01L21/66;(IPC1-7):H01L21/66;H01L21/320 主分类号 G01N1/32
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