BLOCK CELL, DESIGN METHOD OF BLOCK CELL, AND DESIGN AID APPARATUS OF BLOCK CELL

摘要

PROBLEM TO BE SOLVED: To provide a design method of a block cell which is suitable to reduce the skew of clock signals without an increase of a circuit in a semiconductor integrated circuit where block cells coexist. SOLUTION: A plurality of clock terminals C1-C8 are provided in the neighborhood of its periphery inside the block cell 10 and are wired inside the block cell 10 to operate on the basis of the clock signal input from each clock terminals C1-C8. Alternatively, the clock terminal C is provided in the neighborhood of its center inside the block cell 10, and wiring regions LP1-LP4 are provided inside the block cell 10 in order to wire clock signal lines from a plurality of different positions at the periphery of the block cell 10 to the clock terminal C.