| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a structure for efficiently executing an interface with external equipment for a cache DRAM which incorporates a memory controller function. SOLUTION: The semiconductor memory 100, which is a cache DRAM, is provided with a main memory (a DRAM) 10, a cache memory (a SRAM) 11 and a control circuit 25 which controls cache operations. The circuit 25 generates data input output control signals STRB that are commonly used with an external circuit with a prescribed different timing in accordance with a cache hit and a cache mishit. The circuit 25 performs data input and output with the timing responding to the signals STRB. Thus, data exchanges with the external equipment are performed in appropriate timing regardless of the difference in access time at a cache hit or a cache mishit.</p> |
