发明名称 Wire arrayed chip size package and fabrication method thereof
摘要 A chip size package for a semiconductor device according to the present invention is fabricated by: etching a copper film applied on an insulating film tape, except for longitudinal marginal portions of the copper film, metal pattern units thereof which are peripheral to portions corresponding to chip pads of a semiconductor chip and portions thereof connecting the longitudinal marginal portions and the metal pattern units; forming a solder mask on the insulating film tape excluding inner holes of the metal pattern units, the copper film excluding four edge portions of the longitudinal marginal portions thereof and exterior circular marginal portions of the metal pattern units; electroplating portions of surfaces of the metal pattern units on which the solder mask is not formed, for thereby forming metal pattern unit-electroplates; attaching the semiconductor chip to a bottom surface of the insulating film tape; sealing side surfaces and a bottom surface of the semiconductor chip with an epoxy mold compound; etching portions of the insulating film tape formed on the chip pads for thereby exposing the chip pads; electrically connecting by wires the metal pattern unit-electrodes and the corresponding chip pads; and eliminating portions of the copper film remaining at the four edge portions of the longitudinal marginal portions thereof and cutting the resultant insulating film tape to be separated into individual units.
申请公布号 US2002030289(A1) 申请公布日期 2002.03.14
申请号 US20010989494 申请日期 2001.11.21
申请人 HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. 发明人 KWON YONG-TAE
分类号 H01L23/48;H01L21/48;H01L23/31;H01L23/485;H01L23/498;(IPC1-7):H01L23/48;H01L23/52;H01L29/40 主分类号 H01L23/48
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