| 摘要 |
PURPOSE: A method for in a semiconductor device is provided to be capable of compensating space margin and alignment margin between a storage electrode and a bit line. CONSTITUTION: Contact holes for a bit line and a storage electrode are formed by selectively etching the first interlayer dielectric(6) formed on a silicon substrate(1) having a transistor. A bit line contact(10b) and a buffer contact(10a) are formed by filling the first polysilicon layer into the contact holes. The first etch stop layer is formed to expose a bit line formation region. The second etch stop spacer is formed at both sidewalls of the first etch stop layer. After forming the second polysilicon layer on the resultant structure, the first etch stop layer and the second etch stop spacer are removed, thereby forming a bit line pattern(7). After forming a storage electrode contact hole on the buffer contact(10a) via the second interlayer dielectric(8), a storage electrode(9) is formed in the storage electrode contact hole.
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